The output swing of a conventional Voltage Mode Driver (VMD) structure is limited by the power supply of the circuit. For example, a circuit with a one volt (1 V) power supply can produce a one volt differential peak-to-peak (1 VDIFFPP) swing.
However, as semiconductor fabrication processes shrink device sizes smaller and smaller, the supply voltage is typically decreased as well. Consequently, it is difficult to achieve 1 VDIFFPP when supply voltage is less than 1V.
There are several approaches used in the prior art to address this issue.
One approach is to raise the supply voltage. However, raising the supply voltage to overdrive a device often results in a device reliability issue.
Another approach is to adjust the termination to produce a large divided voltage on the receiver side. However, such a change would cause an impedance mismatch, and result in poor signal integrity.
A conventional (PRIOR ART) voltage mode driver (VMD) system 1000 is shown in FIG. 1. Voltage Mode Driver 1100 comprises a pair of p-type transistors 1102, 1106 coupled to n-type transistors 1104, 1108, driving positive output node TXP and negative output node TXN via a supply voltage AVTTR, respectively. The receiver nodes (positive reception node RXP and negative reception node RXN) are modeled as capacitors 1202, 1206 serially connected to resistors 1204, 1208. Assuming the termination is 50 ohms, the receiver's signal amplitude will be AVTTR/4. For example, 1V of AVTTR can produce 0.25V amplitude—which is 1V of VDIFFPP swing.
However, as semiconductor processes shrink, supply voltage sizes are also shrunk. In current state of the art processes, the supply voltage is often below 1V. Consequently, it is difficult to achieve 1V VDIFFPP.
When the supply voltages are raised to obtain a higher VDIFFPP output swing, the device reliability is a concern, as the transistors are overstressed.